MC10H180 Datasheet, PDF (1/4 Pages) ON Semiconductor – Dual 2 Bit Adder/Subtractor

MC10H180
Dual 2-Bit Adder/Subtractor
The MC10H180 is a high–speed, low–power, general–purpose
adder/ subtractor. It is designed to be used in special purpose
adders/subtractors or in high–speed multiplier arrays.
Inputs for each adder are Carry–in, Operand A, and Operand B;
outputs are Sum, Sum and Carry–out. The common select inputs serve
as a control line to Invert A for subtract, and a control line to Invert B.
• Propagation Delay, 1.8 ns Typical, Operand and Select to Output
• Power Dissipation, 360 mW Typicalh180
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
LOGIC DIAGRAM
7
SELA S0
15
9
SELB ^S0
2
5
AO
6
BO
4
CIN COUT
3
SELA S1
14
SELB ^S1
1
11
A1
10
B1
12
CIN COUT
13
VCC = PIN 16
VEE = PIN 8
POSITIVE LOGIC ONLY
  A’ = A SELA = A SELA
  B’ = B SELB = B SELB
S = CIN (A’ B’ + A’ B’) +
CIN(A’ B’ + A’ B’)
COUT = CINA’ + CINB’ + A’ B’
DIP PIN ASSIGNMENT
S1
1
16
VCC
S0
2
15 S0
COUT
3
14 S1
CIN
4
A0
5
B0
6
13
COUT
12 CIN
11 A1
SELA
7
VEE
8
10 B1
9
SELB
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10H180L
AWLYYWW
1
16
MC10H180P
AWLYYWW
1
1
10H180
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H180L
CDIP–16
25 Units/Rail
MC10H180P
PDIP–16
25 Units/Rail
MC10H180FN PLCC–20
46 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10H180/D