MC10H172 Datasheet, PDF (1/5 Pages) ON Semiconductor – Dual Binary to 1−4−Decoder (High)

MC10H172
Dual Binary to 1−4−Decoder
(High)
Description
The MC10H172 is a binary coded 2 line to dual 4 line decoder with
selected outputs high. With either E0 or E1 low, the corresponding
selected 4 outputs are low. The common enable E, when high, forces
all outputs low.
Features
• Propagation Delay, 2 ns Typical
• Power Dissipation 325 mW Typical (same as MECL 10K™)
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K Compatible
• Pb−Free Packages are Available*
E0 14
A9
B7
E 15
E1 2
LOGIC DIAGRAM
10 Q0 3
11 Q0 2
12 Q0 1
13 Q0 0
3 Q1 3
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
4 Q1 2
5 Q1 1
6 Q1 0
DIP
PIN ASSIGNMENT
V_CC1
1
E1
2
Q13
3
Q12
4
Q11
5
Q10
6
B
7
V_EE
8
16
V_CC2
15
E
14
E0
13
Q00
12
Q01
11
Q02
10
Q03
9
A
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 7
http://onsemi.com
MARKING DIAGRAMS*
CDIP−16
L SUFFIX
CASE 620A
16
MC10H172L
AWLYYWW
1
16
16
1
PDIP−16
P SUFFIX
CASE 648
MC10H172P
AWLYYWWG
1
1 20
20 ₁
PLLC−20
FN SUFFIX
CASE 775
10H172G
AWLYYWW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC10H172/D