MC10H161_06 Datasheet, PDF (1/7 Pages) ON Semiconductor – Binary to 1−8 Decoder (Low)

MC10H161
Binary to 1−8 Decoder
(Low)
Description
The MC10H161 provides parallel decoding of a three bit binary
word to one of eight lines. The MC10H161 is useful in high−speed
multiplexer/demultiplexer applications.
The MC10H161 is designed to decode a three bit input word to one
of eight output lines. The MC10H161 output will be low when
selected while all other output are high. The enable inputs, when either
or both are high, force all outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal
parallel path delay times found in other decoder designs. These
devices are ideally suited for multiplexer/demultiplexer applications.
Features
• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 315 mW Typical (same as MECL 10K™)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K Compatible
• Pb−Free Packages are Available*
DIP PIN ASSIGNMENT
http://onsemi.com
MARKING DIAGRAMS*
CDIP−16
L SUFFIX
CASE 620A
16
MC10H161L
AWLYYWW
1
16
16
1
PDIP−16
P SUFFIX
CASE 648
MC10H161P
AWLYYWWG
1
V_CC1
1
16
V_CC2
E0 ^{2 15} E1
Q3 ^{3 14} C
Pin assignment is for Dual−in−Line
Q2
4
13
Package. For PLCC pin assignment, see
Q4 _{the Pin Conversion Tables on page 18 of}
Q1
5
12
Q5
Q0 ^{6 11} Q6
the ON Semiconductor MECL Data
Book (DL122/D).
A ^{7 10} Q7
V_EE
8
9B
LOGIC DIAGRAM
E0 2
E1 15
V_CC1 = Pin 1
V_CC2 = Pin 16
V_EE = Pin 8
A7
B9
6 Q0
5 Q1
ENABLE
INPUTS
E1 E0
TRUTH TABLE
INPUTS
OUTPUTS
C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L L L L L L HH H H HH H
4 Q2 L L L L H H L H H H H H H
L L L H L H H L H H HH H
3 Q3 ^{L L L H H H H H L H H H H}
L L H L L H HH H L HH H
13 Q4
L
L
L
L
H L HH HHHH LHH
HHL H HHHH HL H
L L H HH H HH H H HH L
12 Q5 H X X X X H H H H H H H H
X H X X X H HH H H HH H
11 Q6
SOEIAJ−16
CASE 966
10H161
ALYWG
1 20
20 ₁
PLLC−20
FN SUFFIX
CASE 775
10H161G
AWLYYWW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
C 14
10 Q7
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 7
Publication Order Number:
MC10H161/D