MC10H141 Datasheet, PDF (1/4 Pages) ON Semiconductor – Four-Bit Universal Shift Register

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Four-Bit Universal Shift
Register
MC10H141
The MC10H141 is a four–bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K part with 100%
improvement in propagation delay and operation frequency and no increase in
power supply current.
• Shift frequency, 250 MHz Min
• Power Dissipation, 425 mW Typical
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 5,6,9,11,12,13
Pins 7,10
Pin 4
— 112 — 102 —
— 405 — 255 —
— 416 — 260 —
— 510 — 320 —
112 mA
µA
255
260
320
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Hold Time —
Data, Select
tpd
1.0 2.0 1.0 2.0 1.1 2.1 ns
thold 1.0 — 1.0 — 1.0
—
ns
Set–up Time
Data
Select
tset
ns
1.5 — 1.5 — 1.5
—
3.0 — 3.0 — 3.0
—
Rise Time
Fall Time
Shift Frequency
tr
tf
fshift
0.5 2.4 0.5 2.4 0.5
0.5 2.4 0.5 2.4 0.5
250 — 250 — 250
2.4 ns
2.4 ns
— MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50 ohm resistor to –2.0 volts.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
TRUTH TABLE
SELECT
OPERATING
OUTPUTS
S1 S2 MODE Q0n _{+ 1} Q1n _{+ 1} Q2n _{+ 1} Q3n _{+ 1}
L L Parallel Entry D0
D1
D2
D3
L H Shift Right* Q1n Q2n Q3n
DR
H L Shift Left* DL Q0n Q1n Q2n
H H Stop Shift Q0n Q1n Q2n 32n
* Outputs as exist after pulse appears at “C” input with
input conditions as shown (Pulse Positive transition of
clock input).
DIP
PIN ASSIGNMENT
VCC1
1
Q2
2
Q3
3
C
4
DR
5
D3
6
S2
7
VEE
8
16
VCC2
15
Q1
14
Q0
13
DL
12
D0
11
D1
10
S1
9
D2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
2–131
REV 6