MC10H135_16 Datasheet, PDF (1/5 Pages) ON Semiconductor – Dual J‐K Master‐Slave Flip‐Flop

MC10H135
Dual J‐K Master‐Slave
Flip‐Flop
Description
The MC10H135 is a dual J-K master-slave flip-flop. The device is
provided with an asynchronous set(s) and reset(R). These set and reset
inputs overide the clock.
A common clock is provided with separate J-K inputs. When the
clock is static, the JK inputs do not effect the output. The output states
of the flip flop change on the positive transition of the clock.
Features
• Propagation delay, 1.5 ns Typical
• Power Dissipation, 280 mW Typical/Pkg. (No Load)
• f_tog 250 MHz Max
• Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K™ Compatible
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
16
1
PDIP−16
P SUFFIX
CASE 648−08
20 ₁
PLLC−20
FN SUFFIX
CASE 775−02
MARKING DIAGRAMS*
16
MC10H135P
AWLYYWWG
1
1 20
10H135G
AWLYYWW
PDIP−16
PLLC−20
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
MC10H135FNG
PLLC−20 46 Units / Tube
(Pb-Free)
MC10H135FNR2G PLLC−20 500 Tape & Reel
(Pb-Free)
MC10H135PG
PDIP−16 25 Units / Tube
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 9
Publication Order Number:
MC10H135/D