MC10H135 Datasheet, PDF (1/3 Pages) ON Semiconductor – Dual J-K Master-Slave Flip-Flop

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Master-Slave
Flip-Flop
MC10H135
The MC10H135 is a dual J–K master–slave flip–flop. The device is provided
with an asynchronous set(s) and reset(R). These set and reset inputs overide
the clock.
A common clock is provided with separate J–K inputs. When the clock is
static, the JK inputs do not effect the output. The output states of the flip flop
change on the positive transition of the clock.
• Propagation delay, 1.5 ns Typical
• Power Dissipation, 280 mW
Typical/Pkg. (No Load)
• ftog 250 MHz Max•
• Improved Noise Margin 150
mV (Over Operating Voltage
and Temperature Range)
Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 6, 7, 10, 11
Pins 4, 5, 12, 13
Pin 9
— 75 — 68 —
— 460 — 285 —
— 800 — 500 —
— 675 — 420 —
75 mA
µA
285
500
420
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Set, Reset, Clock
tpd
0.7 2.6 0.7 2.6 0.7 2.6 ns
Rise Time
Fall Time
Set–up Time
Hold Time
Toggle Frequency
tr
tf
tset
thold
ftog
0.7 2.2 0.7 2.2 0.7
0.7 2.2 0.7 2.2 0.7
1.5 — 1.5 — 1.5
1.0 — 1.0 — 1.0
250 — 250 — 250
2.2 ns
2.2 ns
—
ns
—
ns
— MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
S1 5
J1 7
K1 6
R1 4
C9
S2 12
J2 10
K2 11
Q1
2
Q1
3
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Q2
15
Q2
14
R2 13
RS TRUTH TABLE
R
S
Qn _{+ 1}
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
CLOCK J–K TRUTH TABLE*
J
K
Qn _{+ 1}
L
L
Qn
H
L
L
L
H
H
H
H
Qn
*Output states change on
positive transition of clock
for J–K input condition
present.
DIP PIN ASSIGNMENT
VCC1
1
16
VCC2
Q1
2
15 Q2
Q1
3
14 Q2
R1
4
13 R2
S1
5
12 S2
K1
6
11 K2
J1
7
10 J2
VEE
8
9
C
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
2–89
REV 6