MC10H121 Datasheet, PDF (1/4 Pages) ON Semiconductor – 4-WIDE OR-AND / OR-AND GATE

MC10H121
4-Wide OR-AND/OR-AND
Gate
The MC10H121 is a basic logic building block providing the
simultaneous OR–AND/OR–AND–Invert function, useful in data
control and digital multiplexing applications. This MECL 10H part is
a functional/pinout duplication of the standard MECL 10K family
part, with 100% improvement in propagation delay, and no increase in
power– supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 100 mW/Gate Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
LOGIC DIAGRAM
4
5
6
7
9
10
2
3
11
12
13
14
15
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
A1IN
4
A1IN
5
A1IN
6
A2IN
7
VEE
8
16
VCC2
15
A4IN
14
A4IN
13
A4IN
12
A3IN
11
A3IN
10
A2IN, A3IN
9
A2IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620A
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10H121L
AWLYYWW
1
16
MC10H121P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10H121
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H121L
CDIP–16
25 Units/Rail
MC10H121P
PDIP–16
25 Units/Rail
MC10H121FN PLCC–20
46 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 7
Publication Order Number:
MC10H121/D