MC10H117 Datasheet, PDF (1/3 Pages) ON Semiconductor – Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Wide 2-3-Input
OR-AND/OR-AND Gate
MC10H117
The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is a
general purpose logic element designed for use in data control, such as digital
multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H
part is a functional/pinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay, and no increase in power–supply
current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 100 mW/Gate Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 4, 5, 12, 13
Pins 6, 7, 10, 11
Pin 9
— 29 — 26 —
— 465 — 275 —
— 545 — 320 —
— 710 — 415 —
29 mA
µA
275
320
415
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
tpd 0.45 1.35 0.45 1.35 0.5 1.5 ns
Rise Time
tr
0.5 1.5 0.5 1.6 0.5 1.7 ns
Fall Time
tf
0.5 1.5 0.5 1.6 0.5 1.7 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
4
5
3
6
2
7
9
10
11
14
15
12
13
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
A1IN
4
A1IN
5
A2IN
6
A2IN
7
VEE
8
16
VCC2
15
BOUT
14
BOUT
13
B1IN
12
B1IN
11
B2IN
10
B2IN
9
A2IN, B2IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–223
REV 5