MC10H116_16 Datasheet, PDF (1/5 Pages) ON Semiconductor – Triple Line Receiver

MC10H116
Triple Line Receiver
Description
The MC10H116 is a triple differential amplifier designed for use in
sensing differential signals over long lines and is a functional/pinout
duplication of the MC10116, with 100% improvement in propagation
delay and no increase in power supply current. For termination
information see AND8020.
Features
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 85 mW Typ/Pkg (same as MECL 10K™)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K Compatible
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
4
2
5
3
9
6
10
7
12
14
13
15
11
V_BB*
V_CC1 = Pin 1
V_CC2 = Pin 16
V_EE = Pin 8
When input pin with
bubble goes positive
it’s respective output
pin with bubble goes
positive.
*V_BB to be used to supply bias to the MC10H116 only and bypassed
(when used) with 0.01ĂmF to 0.1 mF capacitor to ground (0 V). V_BB can
source < 1.0 mA.
The MC10H116 is designed to be used in sensing differential signals
over long lines. The bias supply (V_BB) is made available to make the
device useful as a Schmitt trigger, or in other applications where a
stable reference voltage is necessary.
Active current sources provide these receivers with excellent
common−mode noise rejection. If any amplifier in a package is not
used, one input of that amplifier must be connected to V_BB to prevent
unbalancing the current−source bias network.
The MC10H116 does not have internal−input pull− down resistors.
This provides high impedance to the amplifier input and facilitates
differential connections.
Applications:
• Low Level Receiver • Voltage Level
• Schmitt Trigger
Interface
Figure 1. Logic Diagram
www.onsemi.com
16
1
20
1
16
1
PDIP−16
PLCC−20
SOIC−16
P SUFFIX
FN SUFFIX
D SUFFIX
CASE 648−08 CASE 775−02 CASE 751B−05
MARKING DIAGRAMS*
16
MC10H116P
AWLYYWWG
1
120
10H116G
AWLYYWW
16
10H116G
AWLYWW
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
V_CC1
1
16
V_CC2
A_OUT
2
15
C_OUT
A_OUT
3
14
C_OUT
A_IN
4
13
C_IN
A_IN
5
12
C_IN
B_OUT
6
11
V_BB
B_OUT
7
10
B_IN
V_EE
8
9
B_IN
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see TND309, the Pin Conversion Tables,
page 9.
Figure 2. Dip Pin Assignment
ORDERING INFORMATION
Device
Package
Shipping^†
MC10H116DG
SOIC−16
(Pb-Free)
48 Units/Tube
MC10H116DR2G
SOIC−16 2500/Tape & Reel
(Pb-Free)
MC10H116FNG
PLCC−20
(Pb-Free)
46 Units/Tube
MC10H116FNR2G
PLCC−20
(Pb-Free)
500/Tape & Reel
MC10H116PG
PDIP−16
(Pb-Free)
25 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 11
Publication Order Number:
MC10H116/D