MC10H113 Datasheet, PDF (1/3 Pages) ON Semiconductor – Quad Exclusive OR Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Exclusive OR Gate
The MC10H113 is a Quad Exclusive OR Gate with an enable common to all
four gates. The outputs may be wire–ORed together to perform a 4–bit
comparison function (A = B). The enable is active LOW.
• Propagation Delay, 1.3 ns Typical
• Power Dissipation 175 mW Typ/Pkg (No Load)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
IE
Input Current High
IinH
Pins 5, 7, 11, 13
Pins 4, 6, 10, 12
Pin 9
— 46 — 42 —
— 430 — 270 —
— 510 — 320 —
— 1100 — 740 —
46 mA
µA
270
320
740
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Data
Enable
tpd
ns
0.4 1.7 0.4 1.8 0.5 1.9
0.5 2.3 0.5 2.4 0.6 2.5
Rise Time
tr
0.5 1.8 0.6 1.9 0.6 2.0 ns
Fall Time
tf
0.5 1.8 0.6 1.9 0.6 2.0 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated
through a 50–ohm resistor to –2.0 volts.
MC10H113
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
E9
4
2 TRUTH TABLE
5
IN E OUTPUT
L LL
L
L HL H
6
H LL H
7
3_{H HL}
L
X XH L
10
14
11
VCC1 = PIN 1
VCC2 = PIN 16
12
15 ^{VEE = PIN 8}
13
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
BOUT
3
AIN
4
AIN
5
BIN
6
BIN
7
VEE
8
16
VCC2
15
DOUT
14
COUT
13
DIN
12
DIN
11
CIN
10
CIN
9
ENABLE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
2–213
REV 6