MC10H105_16 Datasheet, PDF (1/5 Pages) ON Semiconductor – Triple 2‐3‐2‐Input OR/NOR Gate

MC10H105
Triple 2‐3‐2‐Input OR/NOR
Gate
Description
The MC10H105 is a triple 2-3-2-input OR/NOR gate. This
MECL 10H™ part is a functional/pinout duplication of the standard
MECL 10K™ family part, with 100% improvement in propagation
delay, and no increases in power-supply current.
Features
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 25 mW/Gate (same as MECL 10K)
• Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K Compatible
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
4
3
5
2
9
6
10
11
7
13
14
12
15
V_CC1 = Pin 1
V_CC2 = Pin 16
V_EE = Pin 8
Figure 1. Logic Diagram
www.onsemi.com
16
1
PDIP−16
P SUFFIX
CASE 648−08
20 ₁
PLLC−20
FN SUFFIX
CASE 775−02
MARKING DIAGRAMS*
16
MC10H105P
AWLYYWWG
1
1 20
10H105G
AWLYYWW
PDIP−16
PLLC−20
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
V_CC1
1
A_out
2
A_out
3
A_in
4
A_in
5
B_out
6
B_out
7
V_EE
8
16
V_CC2
15
C_out
14
C_out
13
C_in
12
C_in
11
B_in
10
B_in
9
B_in
Pin assignment is for Dual-in-Line Package.
Figure 2. Pin Assignment
ORDERING INFORMATION
Device
MC10H105FNG
MC10H105PG
Package
PLLC−20
(Pb-Free)
PDIP−16
(Pb-Free)
Shipping
46 Units / Tube
25 Units / Tube
© Semiconductor Components Industries, LLC, 2006
1
August, 2016 − Rev. 8
Publication Order Number:
MC10H105/D