MC10H104 Datasheet, PDF (1/3 Pages) ON Semiconductor – Quad 2-Input AND Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input AND Gate
The MC10H104 is a quad 2–input AND gate. One of the gates has both
AND/NAND outputs available. This MECL 10H part is a functional/pinout
duplication of the standard MECL 10K family part, with 100% improvement in
propagation delay, and no increase in power– supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 25 mW/Gate (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
Symbol
Rating
Unit
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
Input Current High
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
IE
IinH
IinL
VOH
VOL
VIH
VIL
— 39 — 35 —
39 mA
— 425 — 265 — 265 µA
0.5 — 0.5 — 0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
AC PARAMETERS
Propagation Delay
tpd
0.4 1.6 0.45 1.75 0.45 1.9 ns
Rise Time
tr
0.5 1.6 0.5 1.7 0.5 1.8 ns
Fall Time
tf
0.5 1.6 0.5 1.7 0.5 1.8 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
MC10H104
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
4
2
5
6
3
7
10
14
11
12
9
13
15
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
BOUT
3
AIN
4
AIN
5
BIN
6
BIN
7
VEE
8
16
VCC2
15
DOUT
14
COUT
13
DIN
12
DIN
11
CIN
10
CIN
9
DOUT
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
2–106
REV 6