MC10EP57 Datasheet, PDF (1/8 Pages) ON Semiconductor – 4:1 Differential Multiplexer

MC10EP57
4:1 Differential Multiplexer
The MC10EP57 is a fully differential 4:1 multiplexer. By leaving
the SEL1 line open (pulled LOW via the input pulldown resistors) the
device can also be used as a differential 2:1 multiplexer with SEL0
input selecting between D0 and D1. The fully differential architecture
of the EP57 makes it ideal for use in low skew applications such as
clock distribution.
The SEL1 is the most significant select line. The binary number
applied to the select inputs will select the same numbered data input
(i.e., 00 selects D0).
Multiple VBB outputs are provided for single-ended or AC coupled
interfaces. In these scenarios, the VBB output should be connected to
the data bar inputs and bypassed via a 0.01µF capacitor to ground.
Note that the VBB output can source/sink up to 0.5mA of current
without upsetting the voltage level. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation
• 350ps Typical Propagation Delays
• Typical Frequency 3.0GHz
• 20–Lead TSSOP Package
• PECL mode: 3.0V to 5.5V VCC with VEE = 0V
• ECL mode: 0V VCC with VEE = –3.0V to –5.5V
• Internal Input Resistors: Pulldown on D, D
• Q Output will default LOW with inputs open or at VEE
• ESD Protection: >2KV HBM, >100V MM
• VBB Outputs
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Useful as Either 4:1 or 2:1 Multiplexer
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 584 devices
VCC SEL1 SEL0 VCC Q
20 19 18 17 16
Q VCC VBB1 VBB2 VEE
15 14 13 12 11
4:1
http://onsemi.com
20
1
TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM
MC10
EP57
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
FUNCTION
D0–3, D0–3
ECL Diff. Data Inputs
SEL0, 1
ECL Mux Select Inputs
VBB1, VBB2
Q, Q
ECL Reference Output Voltage
ECL Data Outputs
VCC
Positive Supply
VEE
Negative, 0 Supply
SEL1
L
L
H
H
FUNCTION TABLE
SEL0
DATA OUT
L
D0, D0
H
D1, D1
L
D2, D2
H
D3, D3
1 2 3 4 5 6 7 8 9 10
VCC D0 D0 D1 D1 D2 D2 D3 D3 VEE
Figure 1. 20–Lead TSSOP (Top View) and Logic Diagram
ORDERING INFORMATION
Device
Package
Shipping
MC10EP57DT
TSSOP
75 Units/Rail
MC10EP57DTR2 TSSOP 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2000
1
April, 2000 – Rev. 2
Publication Order Number:
MC10EP57/D