MC10EP56_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – 3.3V / 5V ECL Dual Differential 2:1 Multiplexer

MC10EP56, MC100EP56
3.3V / 5V ECL Dual
Differential 2:1 Multiplexer
Description
The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple V_BB pins are
provided.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The device features both individual and common select inputs to
address both data path and random logic applications.
The 100 Series contains temperature compensation.
Features
• 360 ps Typical Propagation Delays
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Separate and Common Select
• Q Output Will Default LOW with Inputs Open or at V_EE
• V_BB Outputs
• Pb−Free Packages are Available
http://onsemi.com
MARKING DIAGRAMS*
20
SOIC−20
DW SUFFIX
CASE 751D
1
MC100EP56
AWLYYWWG
TSSOP−20
DT SUFFIX
CASE 948R
QFN−20
MN SUFFIX
CASE 485E
XXXX
EP56
ALYWG
G
20
1 _XXXX
EP56
ALYWG
G
xxxx = MC10 or 100
D
= Date Code
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G, G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 14
Publication Order Number:
MC10EP56/D