MC10EP52_16 Datasheet, PDF (1/11 Pages) ON Semiconductor – ECL Differential Data and Clock D Flip‐Flop

MC10EP52, MC100EP52
3.3 V / 5 V ECL Differential
Data and Clock D Flip‐Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip-flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to V_EE) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
• 330 ps Typical Propagation Delay
• Maximum Frequency = u 4 GHz Typical
• PECL Mode: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode: V_CC = 0 V with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V_EE
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
8
1
SOIC−8 NB
TSSOP−8
DFN8
D SUFFIX
DT SUFFIX MN SUFFIX
CASE 751−07 CASE 948R−02 CASE 506AA
MARKING DIAGRAMS*
8
HEP01
ALYW
G
1
8
KEP01
ALYW
G
1
SOIC−8 NB
8
HP01
ALYWG
G
1
8
KP01
ALYWG
G
1
TSSOP−8
14
14
DFN8
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5T = MC10 Y = Year
3O = MC100 W = Work Week
M = Date Code
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 8
Publication Order Number:
MC10EP52/D