MC10EP52_06 Datasheet, PDF (1/12 Pages) ON Semiconductor – 3.3V / 5V ECL Differential Data and Clock D Flip−Flop

MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip−Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip−flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to V_EE) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
• 330 ps Typical Propagation Delay
• Maximum Frequency u 4 GHz Typical
• PECL Mode: V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode: V_CC = 0 V with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V_EE
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HEP52
ALYW
G
1
8
KEP52
ALYW
G
1
8
HP52
ALYWG
G
1
8
KP52
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5T = MC10 Y = Year
3O = MC100 W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 6
Publication Order Number:
MC10EP52/D