MC10EP51_12 Datasheet, PDF (1/11 Pages) ON Semiconductor – ECL D Flip-Flop with Reset and Differential Clock

MC10EP51, MC100EP51
3.3V / 5V ECL D Flip-Flop
with Reset and Differential
Clock
Description
The MC10/100EP51 is a differential clock D flip−flop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip−flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to V_EE and the CLK input will be biased at V_CC/2.
The 100 Series contains temperature compensation.
Features
• 350 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
HEP51
ALYW
G
1
8
KEP51
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP51
ALYWG
G
1
8
KP51
ALYWG
G
1
1
DFN8
MN SUFFIX
CASE 506AA
1
5S MG
G
1
3N MG
G
H = MC10
A = Assembly Location
K = MC100
L = Wafer Lot
5S = MC10
Y = Year
3N = MC100
W = Work Week
M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
November, 2012 − Rev. 10
Publication Order Number:
MC10EP51/D