MC10EP51 Datasheet, PDF (1/8 Pages) ON Semiconductor – 3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

MC10EP51, MC100EP51
3.3V / 5VĄECL D Flip-Flop
with Reset and Differential
Clock
The MC10/100EP51 is a differential clock D flip–flop with reset.
The device is functionally equivalent to the EL51 and LVEL51
devices.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip–flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EP51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to V_EE and the CLK input will be biased at V_CC/2.
The 100 Series contains temperature compensation.
• 350 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = –3.0 V to –5.5 V
• Open Input Default State
• Safety Clamp on Inputs
http://onsemi.com
MARKING DIAGRAMS*
8
1
SO–8
D SUFFIX
CASE 751
8
HEP51
ALYW
1
8
KEP51
ALYW
1
8
1
TSSOP–8
DT SUFFIX
CASE 948R
8
HP51
ALYW
1
8
KP51
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
MC10EP51D
Package
SO–8
Shipping
98 Units/Rail
MC10EP51DR2
SO–8 2500 Tape & Reel
MC100EP51D
SO–8
98 Units/Rail
MC100EP51DR2 SO–8 2500 Tape & Reel
MC10EP51DT
TSSOP–8 100 Units/Rail
MC10EP51DTR2 TSSOP–8 2500 Tape & Reel
MC100EP51DT TSSOP–8 100 Units/Rail
MC100EP51DTR2 TSSOP–8 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2001
1
April, 2001 – Rev. 3
Publication Order Number:
MC10EP51/D