MC10EP35_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – 3.3V / 5V ECL JK Flip−Flop

MC10EP35, MC100EP35
3.3V / 5V ECL JK Flip−Flop
Description
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip−flop. The J/K data enters the master portion of the
flip−flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
Features
• 410 ps Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V_EE
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HEP35
ALYW
G
1
8
KEP35
ALYW
G
1
8
HP35
ALYWG
G
1
8
KP35
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5R = MC10 Y = Year
3M = MC100 W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 5
Publication Order Number:
MC10EP35/D