MC10EP35 Datasheet, PDF (1/8 Pages) ON Semiconductor – JK Flip Flop

MC10EP35
JK Flip Flop
The MC10EP35 is a higher speed/low voltage version of the EL35
JK flip flop. The J/K data enters the master portion of the flip flop
when the clock is LOW and is transferred to the slave, and thus the
outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
• 300ps Propagation Delay
• High Bandwidth to 3 GHz Typical
• High Bandwidth Output Transistors
• PECL mode: 3.0V to 5.5V VCC with VEE = 0V
• ECL mode: 0V VCC with VEE = –3.0V to –5.5V
W • 75k Internal Input Pulldown Resistors
• Q Output will default LOW with inputs open or at VEE
• ESD Protection: >4KV HBM, >200V MM
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 77 devices
J1
J
8 VCC
K2
CLK 3
RESET 4
K
Flip Flop
R
7Q
6Q
5 VEE
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HEP35
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
FUNCTION
CLK
ECL Clock Inputs
J, K
ECL Signal Inputs
RESET
Q, Q
ECL Asynchronous Reset
ECL Data Outputs
TRUTH TABLE
J
K
RESET CLK
L
L
L
Z
L
H
L
Z
H
L
L
Z
H
H
L
Z
X
X
H
X
Z = LOW to HIGH Transition
Qn+1
Qn
L
H
Qn
L
© Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
ORDERING INFORMATION
Device
Package
Shipping
MC10EP35D
SOIC
98 Units/Rail
MC10EP35DR2 SOIC
2500 Tape & Reel
1
Publication Order Number:
MC10EP35/D