MC10EP33_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – 3.3V / 5V ECL ÷4 Divider

MC10EP33, MC100EP33
3.3V / 5V ECL B4 Divider
Description
The MC10/100EP33 is an integrated B4 divider. The differential
clock inputs.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
Features
• 320 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V_EE
• V_BB Output
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HEP33
ALYW
G
1
8
KEP33
ALYW
G
1
8
HP33
ALYWG
G
1
8
KP33
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5Q = MC10 Y = Year
3L = MC100 W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 9
Publication Order Number:
MC10EP33/D