MC10EP32 Datasheet, PDF (1/8 Pages) ON Semiconductor – ÷2 Divider

MC10EP32
B2 Divider
B The MC10EP32 is an integrated 2 divider. The differential clock
inputs and the VBB allow a differential, single–ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
• 250ps Typical Propagation Delay
• 3 GHz Typical Toggle Frequency
• PECL mode: 3.0V to 5.5V VCC with VEE = 0V
• ECL mode: 0V VCC with VEE = –3.0V to –5.5V
• Internal Input Resistors: Pulldown on D, D
• Q Output will default LOW with inputs open or at VEE
• ESD Protection: >4KV HBM, >200V MM
• VBB Output
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 78 devices
RESET 1
CLK 2
CLK 3
8 VCC
R
7Q
B2
6Q
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HEP32
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
1
*For additional information, see Application Note
AND8002/D
PIN
CLK, CLK
Reset
VBB
Q, Q
VCC
VEE
PIN DESCRIPTION
FUNCTION
ECL Clock Inputs
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
Positive Supply
Negative, 0 Supply
VBB 4
5 VEE
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 1
TRUTH TABLE
CLK CLK RESET
Q
Q
X
X
Z
Z
Z
L
L
H
F
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
ORDERING INFORMATION
Device
Package
Shipping
MC10EP32D
SOIC
98 Units/Rail
MC10EP32DR2 SOIC
2500 Tape & Reel
Publication Order Number:
MC10EP32/D