MC10EP31_16 Datasheet, PDF (1/11 Pages) ON Semiconductor – ECL D Flip‐Flop with Set and Reset

MC10EP31, MC100EP31
3.3 V / 5 V ECL D Flip‐Flop
with Set and Reset
Description
The MC10/100EP31 is a D flip-flop with set and reset. The device is
pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip-flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
Features
• 340 ps Typical Propagation Delay
• Maximum Frequency = > 3 GHz Typical
• PECL Mode Operating Range:
V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V_EE
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
8
1
SOIC−8 NB
TSSOP−8
DFN8
D SUFFIX
DT SUFFIX MN SUFFIX
CASE 751−07 CASE 948R−02 CASE 506AA
MARKING DIAGRAMS*
8
HEP31
ALYW
G
1
8
HP31
ALYWG
G
1
14
8
KEP31
ALYW
G
1
SOIC−8 NB
8
KP31
ALYWG
G
1
TSSOP−8
14
DFN8
H = MC10
A = Assembly Location
K = MC100
L = Wafer Lot
5O = MC10
Y = Year
3J = MC100
W = Work Week
M = Date Code G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 11
Publication Order Number:
MC10EP31/D