MC10EP31 Datasheet, PDF (1/8 Pages) ON Semiconductor – D Flip Flop with Set and Reset

MC10EP31, MC100EP31
3.3V / 5VĄECL D Flip-Flop
with Set and Reset
The MC10/100EP31 is a D flip–flop with set and reset. The device
is pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip–flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
• 340 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = –3.0 V to –5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V_EE
http://onsemi.com
MARKING DIAGRAMS*
8
1
SO–8
D SUFFIX
CASE 751
8
8
HEP31
ALYW
KEP31
ALYW
1
1
8
1
TSSOP–8
DT SUFFIX
CASE 948R
8
HP31
ALYW
1
8
KP31
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC10EP31D
SO–8
98 Units/Rail
MC10EP31DR2
SO–8 2500 Tape & Reel
MC100EP31D
SO–8
98 Units/Rail
MC100EP31DR2 SO–8 2500 Tape & Reel
MC10EP31DT
TSSOP–8 100 Units/Rail
MC10EP31DTR2 TSSOP–8 2500 Tape & Reel
MC100EP31DT TSSOP–8 100 Units/Rail
MC100EP31DTR2 TSSOP–8 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2001
1
April, 2001 – Rev. 5
Publication Order Number:
MC10EP31/D