MC10EP195_06 Datasheet, PDF (1/20 Pages) ON Semiconductor – 3.3V ECL Programmable Delay Chip

MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
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multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
MARKING
10 ps and a net range of up to 10.2 ns. The required delay is selected by
DIAGRAM*
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
Because the EP195 is designed using a chain of multiplexers it has a
LQFP−32
FA SUFFIX
CASE 873A
MCXXX
EP195
AWLYYWWG
32
1
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
1 32
QFN32
MN SUFFIX
CASE 488AM
1
MCXXX
EP195
AWLYYWWG
G
combinations of interconnects between V_EF (pin 7) and V_CF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V_CF and V_EF open. For ECL operation, short V_CF and
V_EF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to V_CF and leave open V_EF pin. The 1.5 V reference
voltage to V_CF pin can be accomplished by placing a 2.2 kW resistor
between V_CF and V_EE for a 3.3 V power supply.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
XXX = 10 or 100
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
The 100 Series contains temperature compensation.
• Maximum Input Clock Frequency >1.2 GHz Typical
• Open Input Default State
• Programmable Range: 0 ns to 10 ns
• Safety Clamp on Inputs
• Delay Range: 2.2 ns to 12.2 ns
• A Logic High on the EN Pin Will Force Q to Logic
• 10 ps Increments
• PECL Mode Operating Range:
Low
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
V_CC = 3.0 V to 3.6 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −3.6 V
Inputs
• V_BB Output Reference Voltage
• Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 16
Publication Order Number:
MC10EP195/D