MC10EP139 Datasheet, PDF (1/14 Pages) ON Semiconductor – 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

MC10EP139, MC100EP139
3.3V / 5V ECL ÷2/4, ÷4/5/6
Clock Generation Chip
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single−ended ECL or, if positive power supplies are used,
LVPECL input signals. In addition, by using the V_BB output, a sinusoidal
source can be AC coupled into the device. If a single−ended input is to be
used, the V_BB output should be connected to the CLK input and bypassed
to ground via a 0.01 mF capacitor.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flip−flop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Upon start−up, the internal flip−flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and the
÷4/5/6 outputs of a single device. All V_CC and V_EE pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
• Maximum Frequency > 1.0 GHz Typical
• 50 ps Output−to−Output Skew
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• V_BB Output
http://onsemi.com
20
1
TSSOP−20
DT SUFFIX
CASE 948E
MARKING
DIAGRAMS*
20
HEP or KEP
139
ALYW
1
20
1
SOIC−20
DW SUFFIX
CASE 751D
20
MCXXXEP139
AWLYYWW
1
HEP = MC10EP
KEP = MC100EP
XXX = 10 or 100
A
= Assembly Location
L,WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
February, 2005 − Rev. 6
Publication Order Number:
MC10EP139/D