MC10EL35_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 5V ECL JK Flip-Flop

MC10EL35, MC100EL35
5V ECL JK Flip-Flop
Description
The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The reset pin is asynchronous and is activated with a logic
HIGH.
The 100 Series contains temperature compensation.
Features
• 525 ps Propagation Delay
• 2.2G Hz Toggle Frequency
• ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE = −4.2 V to
−5.7 V
• Internal Input Pulldown Resistors on J, K, CLK, and R
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL−94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
• Transistor Count = 81 devices
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
HEL35
ALYW
G
1
8
KEL35
ALYW
G
1
8
HL35
ALYWG
G
1
8
KL35
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
14
H = MC10
L = Wafer Lot
K = MC100
Y = Year
4W = MC10
W = Work Week
2L = MC100
M = Date Code
A = Assembly Location G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 6
Publication Order Number:
MC10EL35/D