MC10E457 Datasheet, PDF (1/5 Pages) ON Semiconductor – TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Differential 2:1
Multiplexer
The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals. Multiple VBB pins are provided to
ease AC coupling input signals.
The higher frequency outputs provide the device with a >1.0GHz
bandwidth to meet the needs of the most demanding system clock.
Both, separate selects and a common select, are provided to make the
device well suited for both data path and random logic applications.
The differential inputs have internal clamp structures which will force
the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the
operation of the rest of the device. Note that the input clamp will take
affect only if both inputs fall 2.5V below VCC.
• Differential D and Q; VBB available
• 700ps Max. Propagation Delay
• High Frequency Outputs
• Separate and Common Select
• Extended 100E VEE Range of –4.2V to –5.46V
• Internal 75kΩ Input Pulldown Resistors
MC10E457
MC100E457
TRIPLE DIFFERENTIAL
2:1 MULTIPLEXER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
PIN NAMES
Pin
Dn[0:2]; Dn[0:2]
SEL
COMSEL
VBB
Q[0:2], Q[0:2]
Function
Differential Data Inputs
Individual Select Input
Common Select Input
VBB Reference Output
Differential Data Outputs
FUNCTION TABLE
SEL
H
L
Data
a
b
12/93
© Motorola, Inc. 1996
2–1
Pinout: 28-Lead PLCC (Top View)
SEL2 D2a D2a VBB D2b D2b COMSEL
25 24 23 22 21 20 19
SEL1 26
18 Q2
D1a 27
D1a 28
17 Q2
16 VCC
VEE ¹
15 Q1
VBB 2
D1b 3
14 Q1
13 Q0
D1b 4
12 Q0
5 6 7 8 9 10 11
SEL0 D0a D0a VBB D0b D0b VCCO
* All VCC and VCCO pins are tied together on the die.
REV 2