MC10E452 Datasheet, PDF (1/4 Pages) ON Semiconductor – 5-BIT DIFFERENTIAL REGISTER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
5ĆBit Differential Register
The MC10E/100E452 is a 5-bit differential register with differential data
(inputs and outputs) and clock. The registers are triggered by a positive
transition of the positive clock (CLK) input. A high on the Master Reset
(MR) asynchronously resets all registers so that the Q outputs go LOW.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
The fully differential design of the device makes it ideal for very high
frequency applications where a registered data path is necessary.
• Differential D, CLK and Q; VBB Reference Available
• 1100MHz Min. Toggle Frequency
• Asynchronous Master Reset
• Extended 100E VEE Range of – 4.2V to – 5.46V
Pinout: 28-Lead PLCC (Top View)
D3 D3 D4 D4 VCCO Q4 Q4
25 24 23 22 21 20 19
MR 26
18 Q3
CLK 27
17 Q3
CLK 28
16 VCC
VEE ¹
15 Q2
VBB 2
D2 3
D2 4
14 Q2
13 Q1
12 Q1
5 6 7 8 9 10 11
D1 D1 D0 D0 VCCO Q0 Q0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D[0:4], D[0:4]
MR
CLK, CLK
VBB
Q[0:4], Q[0:4]
Function
Differential Data Inputs
Master Reset Input
Differential Clock Input
VBB Reference Output
Differential Data Outputs
12/93
© Motorola, Inc. 1996
2–1
MC10E452
MC100E452
5-BIT DIFFERENTIAL
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0
D0
D
Q
Q0
Q0
R
D1
D1
D
Q
Q1
Q1
R
D2
D2
D
Q
Q2
Q2
R
D3
D3
D
Q
Q3
Q3
R
D4
D4
D
Q
Q4
Q4
CLK
R
CLK
MR
VBB
REV 2