MC10E445_06 Datasheet, PDF (1/13 Pages) ON Semiconductor – 5V ECL 4-Bit Serial/Parallel Converter

MC10E445, MC100E445
5V ECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
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both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
PLCC−28
Two selectable serial inputs provide a loopback capability for testing
FN SUFFIX
purposes when the device is used in conjunction with the E446 parallel to
CASE 776
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn−1. For each additional
MARKING DIAGRAM*
shift required an additional pulse must be applied to the SYNC input.
1 28
Asserting the SYNC input will force the internal clock dividers to
“swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
MCxxxE445FNG
AWLYYWW
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
scheme using two E445’s. When cascaded in an 8-bit conversion scheme
xxx
= 10 or 100
the devices will not operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for more information on
cascading the E445.
Upon power-up the internal flip-flops will attain a random state. To
synchronize multiple E445’s in a system the master reset must be asserted.
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
The V_BB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
*For additional marking information, refer to
Application Note AND8002/D.
input is connected to V_BB as a switching reference voltage. V_BB may also
rebias AC coupled inputs. When used, decouple V_BB and V_CC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
ORDERING INFORMATION
See detailed ordering and shipping information in the package
not used, V_BB should be left open.
dimensions section on page 11 of this data sheet.
The 100 Series contains temperature compensation.
Features
• On-Chip Clock ÷4 and ÷8
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• 2.0 Gb/s Data Rate Capability
• Meets or Exceeds JEDEC Spec EIA/JESD78
• Differential Clock and Serial Inputs
IC Latchup Test
• V_BB Output for Single-Ended Input Applications
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
• Asynchronous Data Synchronization
For Additional Information, see Application Note
• Mode Select to Expand to 8-Bits
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 528 devices
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V
with V_EE = 0 V
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 12
Publication Order Number:
MC10E445/D