MC10E431_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – 5V ECL 3-Bit Differential Flip-Flop

MC10E431, MC100E431
5V ECL 3-Bit Differential
Flip-Flop
Description
The MC10E/100E431 is a 3-bit flip-flop with differential clock,
data input and data output.
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The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with
a level controlled set/reset).
PLCC−28
FN SUFFIX
CASE 776
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
MARKING DIAGRAM*
The differential input structures are clamped so that the inputs of
1 28
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
MCxxxE431FNG
AWLYYWW
input clamps only operate when both inputs fall to 2.5 V below V_CC.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The 100 Series contains temperature compensation.
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
Features
• Edge-Triggered Asynchronous Set and Reset
*For additional marking information, refer to
Application Note AND8002/D.
• Differential D, CLK and Q; V_BB Reference Available
• 1100 MHz Min. Toggle Frequency
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
with V_EE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Machine Model; > 200 V
Charged Device Model; > 2 kV
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Oxygen Index: 28 to 34
• Transistor Count = 348 devices
• Pb−Free Packages are Available*
Latchup Test
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 10
Publication Order Number:
MC10E431/D