MC10E431 Datasheet, PDF (1/4 Pages) ON Semiconductor – 3-BIT DIFFERENTIAL FLIP-FLOP

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3ĆBit Differential FlipĆFlop
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data
input and data output.
The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with a
level controlled set/reset).
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
• Edge-Triggered Asynchronous Set and Reset
• Differential D, CLK and Q; VBB Reference Available
• 1100MHz Min. Toggle Frequency
• Extended 100E VEE Range of – 4.2V to – 5.46V
Pinout: 28-Lead PLCC (Top View)
VBB CLK2 CLK2 D2 D2 R2 S2
25 24 23 22 21 20 19
CLK1 ₂₆
18 _Q2
CLK1 ₂₇
17 Q2
R1 28
16 _VCC
VEE 1
15 _Q1
S1 2
14 _Q1
D1 3
13 _Q0
D1 ₄
12 Q0
5 6 7 8 9 10 11
CLK0 CLK0 D0 D0 R0 S0 VCCO
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
S[0:2]
R[0:2]
VBB
Q[0:2], Q[0:2]
Function
Differential Data Inputs
Differential Clock
Edge Triggered Set Inputs
Edge Triggered Reset Input
VBB Reference Output
Differential Data Outputs
5/95
© Motorola, Inc. 1996
2–1
MC10E431
MC100E431
3-BIT DIFFERENTIAL
FLIP-FLOP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
S0
D0
D0
S
D
Q
Q0
CLK0
CLK0
R0
S1
D1
D1
Q
Q0
R
S
D
Q
Q1
CLK1
CLK1
R1
S2
D2
D2
Q
Q1
R
S
D
Q
Q2
CLK2
CLK2
R2
Q
Q2
R
VBB
REV 3