MC10E416 Datasheet, PDF (1/4 Pages) ON Semiconductor – QUINT DIFFERENTIAL LINE RECEIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Differential Line
Receiver
The MC10E416/100E416 is a 5-bit differential line receiving device.
The 2.0GHz of bandwidth provided by the high frequency outputs makes
the device ideal for buffering of very high speed oscillators.
A VBB pin is available to AC couple an input signal to the device. More
information on AC coupling can be found in the design handbook section
of this data book.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will force
the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the
operation of the rest of the device. Note that the input clamp will take
affect only if both inputs fall 2.5V below VCC.
• Differential D and Q; VBB available
• 600ps Max. Propagation Delay
• High Frequency Outputs
• 2 Stages of Gain
• Extended 100E VEE Range of – 4.2V to – 5.46V
• Internal 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D3 D4 D4 VCCO Q4 Q4 VCCO
25 24 23 22 21 20 19
D3 26
18 Q3
D2 27
17 Q3
D2 28
16 VCC
VEE 1
15 Q2
VBB 2
14 Q2
D0 3
13 VCCO
D0 4
12 Q1
5 6 7 8 9 10 11
D1 D1 VCCO Q0 Q0 VCCO Q1
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D[0:4], D[0:4]
Q[0:4], Q[0:4]
Function
Differential Data Inputs
Differential Data Outputs
12/93
© Motorola, Inc. 1996
2–1
MC10E416
MC100E416
QUINT DIFFERENTIAL
LINE RECEIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D4
Q4
VBB
REV 2