MC10E256 Datasheet, PDF (1/5 Pages) ON Semiconductor – 3-BIT 4:1 MUX-LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3ĆBit 4:1 MuxĆLatch
The MC10E/100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls are
provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic HIGH
on LEN latches the outputs. The Master Reset (MR) overrides all other
controls to set the Q outputs LOW.
• 950ps Max. D to Output
• 850ps Max. LEN to Output
• Split Select
• Differential Outputs
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D1b D1a D2d D2c D2b D2a VCCO
25 24 23 22 21 20 19
SEL1A 26
18 Q2
SEL1B 27
17 Q2
SEL2 28
16 VCC
VEE 1
15 Q1
LEN 2
14 Q1
MR 3
13 VCCO
D1c 4
12 Q0
5 6 7 8 9 10 11
D1d D0a D0b D0c D0d VCCO Q0
* All VCC and VCCO pins are tied together on the die.
MC10E256
MC100E256
3-BIT 4:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
FUNCTION TABLE
Pin
State
SEL2
H
SEL1A
H
SEL1B
H
Operation
Output c/d Data
Input d Data
Input b Data
12/93
© Motorola, Inc. 1996
2–1
PIN NAMES
Pin
D0x – D2x
SEL1A, SEL1B
SEL2
LEN
MR
Q0, Q0 – Q2, Q2
Function
Data Inputs
First-stage Select Inputs
Second-stage Select input
Latch Enable
Master Reset
Data Outputs
REV 2