MC10E212 Datasheet, PDF (1/4 Pages) ON Semiconductor – 3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3ĆBit Scannable Registered
Address Driver
The MC10E/100E212 is a scannable registered ECL driver typically
used as a fan-out memory address driver for ECL cache driving. In a VLSI
array based CPU design, use of the E212 allows the user to conserve
array output cell functionality and also output pins.
The input shift register is designed with control logic which greatly
facilitates its use in boundary scan applications.
• Scannable Version E112 Driver
• 1025ps Max. CLK to Output
• Dual Differential Outputs
• Master Reset
• Extended 100E VEE Range of – 4.2V to – 5.46V
• Internal 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
SHIFT MR NC S-OUTVCCO Q2b Q2a
25 24 23 22 21 20 19
LOAD ²⁶
18 Q2b
CLK 27
17 Q2a
D2 28
16 VCC
VEE 1
15 Q1b
D1 2
14 Q1a
D0 3
13 Q1b
S-IN 4
12 Q1a
5 6 7 8 9 10 11
NC VCCO Q0a Q0b Q0a Q0b VCCO
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 – D2
S-IN
LOAD
SHIFT
CLK
MR
S-OUT
Q[0:2]a, Q[0:2]b
Q[0:2]a, Q[0:2]b
Function
Data Inputs
Scan Input
LOAD/HOLD Control
Scan Control
Clock
Reset
Scan Output
True Outputs
Inverting Outputs
12/93
© Motorola, Inc. 1996
2–1
D2
D1
D0
S-IN
LOAD
SHIFT
CLK
MR
MC10E212
MC100E212
3-BIT SCANNABLE
REGISTERED
ADDRESS DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D
Q
S-OUT
Q2b
Q2a
Q2a
Q2b
Q1b
D
Q1a
Q
Q1a
Q1b
Q0b
D
Q0a
Q
Q0a
Q0b
REV 2