MC10E211_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – 5V ECL 1:6 Differential Clock Distribution Chip

MC10E211, MC100E211
5V ECL 1:6 Differential
Clock Distribution Chip
Description
The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications.
The E211 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open in which case it will be
pulled LOW by the input pulldown resistor) the SEL pin will select the
differential clock input.
Both a common enable and individual output enables are provided.
When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enabling function is
synchronous so that the outputs will only be enabled/disabled when
the outputs are already in the LOW state. In this way the problem of
runt pulse generation during the disable operation is avoided. Note that
the internal flip flop is clocked on the falling edge of the input clock
edge, therefore all associated specifications are referenced to the
negative edge of the CLK input.
The output transitions of the E211 are faster than the standard
ECLinPS edge rates. This feature provides a means of distributing
higher frequency signals than capable with the E111 device. Because
of these edge rates and the tight skew limits guaranteed in the
specification, there are certain termination guidelines which must be
followed. For more details on the recommended termination schemes
please refer to the applications information section of this data sheet.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The 100 Series contains temperature compensation.
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE211FNG
AWLYYWW
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Features
• Guaranteed Low Skew Specification
• Synchronous Enabling/Disabling
• Multiplexed Clock Inputs
• V_BB Output for Single−Ended Use
• Common and Individual Enable/Disable Control
• High Bandwidth Output Transistors
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE =
−4.2 V to −5.7 V
• Internal Input 75 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 457 devices
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 12
Publication Order Number:
MC10E211/D