MC10E195 Datasheet, PDF (1/5 Pages) ON Semiconductor – PROGRAMMABLE DELAY CHIP

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MC10E195/D
Programmable Delay Chip
The MC10E/100E195 is a programmable delay chip (PDC) designed
primarily for clock de-skewing and timing adjustment. It provides variable
delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.
Because the delay programmability of the E195 is achieved by purely
differential ECL gate delays the device will operate at frequencies of >1.0
GHz while maintaining over 600 mV of output swing.
The E195 thus offers very fine resolution, at very high frequencies, that
is selectable entirely from a digital input allowing for very accurate system
clock timing.
An eighth latched input, D7, is provided for cascading multiple PDC’s
for increased programmable range. The cascade logic allows full control
of multiple PDC’s, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.
• 2.0ns Worst Case Delay Range
• ≈20ps/Delay Step Resolution
• >1.0GHz Bandwidth
• On Chip Cascade Circuitry
• Extended 100E VEE Range of –4.2 to –5.46V
• 75KΩ Input Pulldown Resistors
PIN NAMES
Pin
Function
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
MC10E195
MC100E195
PROGRAMMABLE
DELAY CHIP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D2 D3 D4 D5 D6 D7 NC
25 24 23 22 21 20 19
26 D1
NC 18
27 D0
NC 17
28 LEN
1 ^VEE
2 ^IN
Pinout:
28-Lead PLCC
(Top View)
VCC 16
VCCO 15
Q 14
3 ^IN
Q 13
4 ^VBB
5 6 78
NC NC EN
VCCO 12
9 10 11
VBB
IN
11 ₀
0
IN
1
1
EN
* 1.25
* 1.5
LEN
SET MIN
SET MAX
LOGIC DIAGRAM – SIMPLIFIED
0
11
0
1 11
0
4 GATES
1
7 BIT LATCH
0
8 GATES
1
16 GATES
LEN Q
LATCH
D
0
1
0
11
CASCADE
D0
D1
D2
D3
D4
D5
D6
* DELAYS ARE 25% OR 50% LONGER THAN
* STANDARD (STANDARD ≈ 80 PS)
04/99
© Motorola, Inc. 1999
2–1
D7
REV 3
Q
Q
CASCADE
CASCADE