MC10E175 Datasheet, PDF (1/4 Pages) ON Semiconductor – 9-BIT LATCH WITH PARITY

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9ĆBit Latch With Parity
The MC10E/100E175 is a 9-bit latch. It also features a tenth latched
output, ODDPAR, which is formed as the odd parity of the nine data
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by using D8 as the
parity-type select (L = even parity, H = odd parity), and using ODDPAR as
the byte parity output.
The LEN pin latches the data when asserted with a logical high and
makes the latch transparent when placed at a logic low level.
• 9-Bit Latch
• Parity Detection/Generation
• 800ps Max. D to Output
• Reset
• Extended 100E VEE Range of – 4.2V to – 5.46V
• Internal 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D6 D7 D8 VCCO Q8 Q7 VCCO
25 24 23 22 21 20 19
D5 26
18 Q6
D4 27
17 Q5
D3 28
16 VCC
VEE ¹
15 Q4
LEN 2
MR 3
14 Q3
D0
13 VCCO
D2 4
12 Q2
5 6 7 8 9 10 11
D1 D0 VCCO
Q0 VCCO Q1
D8
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
Function
D0 – D8
LEN
Data Inputs
Latch Enable
MR
Master Reset
Q0 – Q8
Data Outputs
LEN
ODDPAR
Parity Output
MR
MC10E175
MC100E175
9-BIT LATCH
WITH PARITY
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
DQ
Q0
EN
R
BITS
1–7
DQ
Q8
EN
R
DQ
EN
R
ODDPAR
12/93
© Motorola, Inc. 1996
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