MC10E167 Datasheet, PDF (1/4 Pages) ON Semiconductor – 6-BIT 2:1 MUX-REGISTER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
6ĆBit 2:1 MuxĆRegister
The MC10E/100E167 contains six 2:1 multiplexers followed by D
flip-flops with single-ended outputs. Input data are selected by the Select
control, SEL. The selected data are transferred to the flip-flop outputs by
a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset
(MR) pin asynchronously forces all Q outputs LOW.
• 1000MHz Min. Operating Frequency
• 800ps Max. Clock to Output
• Single-Ended Outputs
• Asynchronous Master Resets
• Dual Clocks
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D5a D4b D4a D3b D3a NC VCCO
25 24 23 22 21 20 19
D5b 26
18 Q5
CLK1 27
17 Q4
CLK2 ²⁸
16 VCC
VEE ¹
15 Q3
MR ²
14 Q2
SEL ³
13 VCCO
D0a 4
12 Q1
5 6 7 8 9 10 11
D0b D1a D1b D2a D2b VCCO Q0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a – D5a
D0b – D5b
SEL
CLK1, CLK2
MR
Q0 – Q5
FUNCTIONS
SEL
H
L
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
Data
a
b
12/93
© Motorola, Inc. 1996
2–1
MC10E167
MC100E167
6-BIT 2:1
MUX-REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
SEL
CLK1
CLK2
MR
LOGIC DIAGRAM
MUX
SEL
DQ
Q0
R
MUX
SEL
D ^{Q Q1}
R
MUX
SEL
D ^{Q Q2}
R
MUX
SEL
Q
D
Q3
R
MUX
SEL
D ^{Q Q4}
R
MUX
SEL
D ^{Q Q5}
R
REV 2