MC10E160 Datasheet, PDF (1/4 Pages) ON Semiconductor – 12-BIT PARITY GENERATOR/CHECKER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
12ĆBit Parity
Generator/Checker
The MC10E/100E160 is a 12-bit parity generator/checker. The Q
output is HIGH when an odd number of inputs are HIGH. A HIGH on the
Enable input (EN) forces the Q output LOW.
The E160 also features an output register. Multiplexers direct the
register input, giving the option of holding present data by asserting
HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT
HIGH. The output register itself is clocked by a positive edge on CLK1 or
CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y
output LOW.
• Provides Odd-HIGH Parity of 12 Inputs
• Shiftable Output Register with Hold
• 900ps Max. D to Q/Q Output
• Enable
• Asynchronous Register Reset
• Dual Clocks
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D4 D3 D2 D1 D0 EN VCCO
25 24 23 22 21 20 19
D5 26
18 Q
D6 27
17 Q
D7 28
16 VCC
VEE 1
15 Y
D8 2
14 Y
D9 3
13 VCCO
D10 4
12 NC
5 6 7 8 9 10 11
D11 HOLD S-IN SHIFT CLK1 CLK2 R
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
Function
D0 – D11
S-IN
EN
HOLD
SHIFT
CLK1, CLK2
R
Q, Q
Y, Y
Data Inputs
Serial Data Input
Enable, active LOW
Hold, active LOW
Shift, active HIGH
Clock Inputs
Reset Inputs
Direct Output
Register Output
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
EN
HOLD
S-IN
SHIFT
CLK1
CLK2
R
12/93
© Motorola, Inc. 1996
2–1
MC10E160
MC100E160
12-BIT PARITY
GENERATOR/CHECKER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
Q
0
0
D
Y
MUX
MUX
1 _SEL
1 _SEL
R
Y
REV 2