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MC10E155_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 5V ECL 6−Bit 2:1 Mux−Latch | |||
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MC10E155, MC100E155
5V ECL 6âBit 2:1
MuxâLatch
Description
The MC10E/100E155 contains six 2:1 multiplexers followed by
transparent latches with singleâended outputs. When both Latch
Enables (LEN1, LEN2) are LOW, the latch is transparent, and output
data is controlled by the multiplexer select control, SEL. A logic
HIGH on either LEN1 or LEN2 (or both) latches the outputs. The
Master Reset (MR) overrides all other controls to set the Q outputs
LOW.
The 100 Series contains temperature compensation.
Features
⢠850 ps Max. LEN to Output
⢠825 ps Max. D to Output
⢠SingleâEnded Outputs
⢠Asynchronous Master Reset
⢠Dual LatchâEnables
⢠PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
⢠NECL Mode Operating Range: VCC = 0 V
with VEE = â4.2 V to â5.7 V
⢠Internal Input 50 kW Pulldown Resistors
⢠ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
⢠Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
⢠Moisture Sensitivity Level:
Pb = 1
PbâFree = 3
For Additional Information, see Application Note AND8003/D
⢠Flammability Rating: UL 94 Vâ0 @ 0.125 in,
Oxygen Index: 28 to 34
⢠Transistor Count = 239 Devices
⢠PbâFree Packages are Available*
http://onsemi.com
PLCCâ28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE155FNG
AWLYYWW
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW = Work Week
G
= PbâFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our PbâFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 â Rev. 8
Publication Order Number:
MC10E155/D
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