MC10E155 Datasheet, PDF (1/4 Pages) ON Semiconductor – 6-BIT 2:1 MUX-LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
6ĆBit 2:1 MuxĆLatch
The MC10E/100E155 contains six 2:1 multiplexers followed by
transparent latches with single-ended outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output data is
controlled by the multiplexer select control, SEL. A logic HIGH on either
LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)
overrides all other controls to set the Q outputs LOW.
• 850ps Max. LEN to Output
• 825ps Max. D to Output
• Single-Ended Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
D5a D4b D4a D3b D3a NC VCCO
25 24 23 22 21 20 19
D5b ₂₆
18 Q5
LEN1 ₂₇
17 Q4
LEN2 28
16 _VCC
VEE 1
15 _Q3
MR 2
14 _Q2
SEL 3
13 _VCCO
D0a ₄
12 Q1
5 6 7 8 9 10 11
D0b D1a D1b D2a D2b VCCO Q0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a – D04
D0b – D4b
SEL
LEN1, LEN2
MR
Q0 – Q4
TRUTH TABLE
SEL
H
L
5/95
© Motorola, Inc. 1996
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
Outputs
Data
a
b
2–1
MC10E155
MC100E155
6-BIT 2:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0a
MUX
D0b
SEL
Q
D
Q0
EN
R
D1a
MUX
D1b
SEL
Q
D
Q1
EN
R
D2a
MUX
D2b
SEL
Q
D
Q2
EN
R
D3a
MUX
D3b
SEL
Q
D
Q3
EN
R
D4a
D4b
D5a
D5b
SEL
LEN1
LEN2
MR
MUX
SEL
MUX
SEL
DQ
Q4
EN
R
DQ
Q5
EN
R
REV 3