MC10E154 Datasheet, PDF (1/4 Pages) ON Semiconductor – 5-BIT 2:1 MUX-LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
5ĆBit 2:1 MuxĆLatch
The MC10E/100E154 contains five 2:1 multiplexers followed by
transparent latches with differential outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output data is
controlled by the multiplexer select control, SEL. A logic HIGH on either
LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)
overrides all other controls to set the Q outputs LOW.
• 850ps Max. LEN to Output
• 825ps Max. D to Output
• Differential Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
MC10E154
MC100E154
5-BIT 2:1
MUX-LATCH
Pinout: 28-Lead PLCC (Top View)
D4b D4a D3b D3a VCCO Q4 Q4
25 24 23 22 21 20 19
SEL ₂₆
18 Q3
LEN1 ₂₇
17 Q3
LEN2 28
16 VCC
VEE 1
15 Q2
MR 2
14 Q2
D0a 3
13 Q1
D0b ₄
12 Q1
5 6 7 8 9 10 11
D1a D1b D2a D2b VCCO Q0 Q0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0a – D4a
D0b – D4b
SEL
LEN1, LEN2
MR
Q0 – Q4
Q0 – Q4
TRUTH TABLE
SEL
H
L
12/93
© Motorola, Inc. 1996
Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
True Outputs
Inverted Outputs
Data
a
b
2–1
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
SEL
LEN1
LEN2
MR
LOGIC DIAGRAM
MUX
SEL
Q
D
Q0
EN
R
Q
Q0
MUX
SEL
Q
D
Q1
EN
R
Q
Q1
MUX
SEL
DQ
Q2
EN
R
Q
Q2
MUX
SEL
DQ
Q3
EN
R
Q
Q3
MUX
SEL
DQ
Q4
EN
R
Q
Q4
REV 2