MC10E142 Datasheet, PDF (1/4 Pages) ON Semiconductor – 9-BIT SHIFT REGISTER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9ĆBit Shift Register
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity
applications in mind. The E142 performs serial/parallel in and
serial/parallel out, shifting in one direction. The nine inputs D0 – D8
accept parallel input data, while S-IN accepts serial input data. The Qn
outputs do not need to be terminated for the shift operation to function. To
minimize noise and power, any Q output not used should be left
unterminated.
• 700MHz Min. Shift Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The SEL (Select) input pin is used to switch between the two modes of
operation — SHIFT and LOAD. The shift direction is from bit 0 to bit 8.
Input data is accepted by the registers a set-up time before the positive
going edge of CLK1 or CLK2; shifting is also accomplished on the positive
clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets
all the resisters to zero.
SEL D8 D7 D6 D5 VCCO Q8
25 24 23 22 21 20 19
MR ₂₆
18 Q7
CLK1 ₂₇
17 Q6
CLK2 28
VEE ₁
S-IN 2
D0 3
Pinout: 28-Lead PLCC
(Top View)
16 _VCC
15 _Q5
14 _VCCO
13 _Q4
D1 ₄
12 Q3
5 6 7 8 9 10 11
D2 D3 D4 VCCO Q0 Q1 Q2
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 – D8
S-IN
SEL
CLK1, CLK2
MR
Q0 – Q8
FUNCTIONS
SEL
L
H
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
Load
Shift
Function
Mode
12/93
© Motorola, Inc. 1996
2–1
MC10E142
MC100E142
9-BIT SHIFT
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
S-IN
D0
1
0
DQ
Q0
D1
1
0
Q
D
Q1
D2
1
0
Q
D
Q2
1
DQ
Q3
D3
0
1
DQ
Q8
D8
0
SEL
CLK1
CLK2
MR
REV 2