MC10E141 Datasheet, PDF (1/4 Pages) ON Semiconductor – 8-BIT SHIFT REGISTER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8ĆBit Shift Register
The MC10E/100E141 is an 8-bit full-function shift register. The E141
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D0 – D7 accept parallel input data, while
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
• 700MHz Min. Shift Frequency
• 8-Bit
• Full-Function, Bi-Directional
• Asynchronous Master Reset
• Pin-Compatible with E241
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
MC10E141
MC100E141
8-BIT SHIFT
REGISTER
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
Pinout: 28-Lead PLCC (Top View)
SEL0 DL D7 D6 D5 VCCO Q7
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
25 24 23 22 21 20 19
SEL1 26
18 Q6
CLK 27
17 Q5
MR 28
16 VCC
VEE 1
15 NC
DR 2
D0 3
D1 4
14 VCCO
13 Q4
12 Q3
5 6 7 8 9 10 11
D2 D3 D4 VCCO Q0 Q1 Q2
* All VCC and VCCO pins are tied together on the die.
EXPANDED FUNCTION TABLE
FUNCTION TABLE
SEL0 SEL1
Function
L
L Load
L
H Shift Right (Dn to Dn+1)
H
L
Shift Left (Dn to Dn _–1)
H
H Hold
PIN NAMES
Pin
D0 – D7
DL, DR
SEL0, SEL1
CLK
Q0 – Q7
MR
Function
Parallel Data Inputs
Serial Data Inputs
Mode Select In Inputs
Clock
Data Outputs
Master Reset
Function
DL DR SEL0 SEL1 MR CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Load
X
X
L
Shift Right
X
L
L
X
H
L
Shift Left
L
X
H
H
X
H
Hold
X
X
H
X
X
H
Reset
X
X
X
L
L
Z
D0 D1 D2 D3 D4 D5 D6 D7
H
L
Z
L
Q0 Q1 Q2 Q3 Q4 Q5 Q6
H
L
Z
H
L
Q0 Q1 Q2 Q3 Q4 Q5
L
L
Z
L
Q0 Q1 Q2 Q3 Q4 Q5
L
L
L
Z
Q0 Q1 Q2 Q3 Q4 Q5
L
H
H
L
Z
Q0 Q1 Q2 Q3 Q4 Q5
L
H
H
L
Z
Q0 Q1 Q2 Q3 Q4 Q5
L
H
X
H
X
L
L
L
L
L
L
L
L
7/96
© Motorola, Inc. 1996
2–1
REV 3