MC10E131 Datasheet, PDF (1/4 Pages) ON Semiconductor – 4-BIT D FLIP-FLOP

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4ĆBit D FlipĆFlop
The MC10E/100E131 is a quad master-slave D-type flip-flop with
differential outputs. Each flip-flop may be clocked separately by holding
Common Clock (CC) LOW and using the Clock Enable (CE) inputs for
clocking. Common clocking is achieved by holding the CE inputs LOW
and using CC to clock all four flip-flops. In this case, the CE inputs perform
the function of controlling the common clock, to each flip-flop.
Individual asynchronous resets are provided (R). Asynchronous set
controls (S) are ganged together in pairs, with the pairing chosen to
reflect physical chip symmetry.
Data enters the master when both CC and CE are LOW, and transfers
to the slave when either CC or CE (or both) go HIGH.
• 1100MHz Min. Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
R3 D2 CE2 R2 VCCO Q3 Q3
25 24 23 22 21 20 19
CE3 26
18 Q2
D3 27
17 Q2
S12 28
VEE ¹
16 VCC
15 Q1
CC 2
14 Q1
S03 3
13 Q0
D0 4
12 Q0
5 6 7 8 9 10 11
CE0 R0 D1 CE1 R1 NC VCCO
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin
D0 – D3
CE0 – CE3
R0 – R3
CC
S03, S12
Q0 – Q3
Q0 – Q3
Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
7/96
© Motorola, Inc. 1996
2–1
MC10E131
MC100E131
4-BIT
D FLIP-FLOP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D3
CE3
R3
D2
CE2
R2
S03
S12
CC
R1
CE1
D1
S
D
Q
Q3
Q
R
Q3
S
D
Q
Q2
Q
R
Q2
R
Q
Q1
D
Q
Q1
S
R0
CE0
RQ
Q0
D0
D
Q
S
Q0
REV 3