MC10E116 Datasheet, PDF (1/4 Pages) ON Semiconductor – QUINT DIFFERENTIAL LINE RECEIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Differential Line
Receiver
MC10E116
MC100E116
The MC10E/100E116 is a quint differential line receiver with
emitter-follower outputs. An internally generated reference supply (VBB)
is available for single-ended reception.
• 500ps Max. Propagation Delay
• VBB Supply Output
• Dedicated VCCO Pin for Each Receiver
• Extended 100E VEE Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
QUINT DIFFERENTIAL
LINE RECEIVER
Active current sources plus a deep collector feature of the MOSAIC III
process provide the receivers with excellent common-mode noise
rejection. Each receiver has a dedicated VCCO supply lead, providing
optimum symmetry and stability.
The receiver design features clamp circuitry to cause a defined state if
both the inverting and non-inverting inputs are left open; in this case the Q
output goes LOW, while the Q output goes HIGH. This feature makes the
device ideal for twisted pair applications.
If both inverting and non-inverting inputs are at an equal potential of
> –2.5V, the receiver does not go to a defined state, but rather
current-shares in normal differential amplifier fashion, producing output
voltage levels midway between HIGH and LOW, or the device may even
oscillate.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
The device VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only.
When using for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor. Please refer to the interface
section of the design guide for information on using the E116 in specialized applications.
The E116 features input pull-down resistors, as does the rest of the ECLinPS family. For applications which require
bandwidths greater than that of the E116, the E416 device may be of interest.
PIN NAMES
Pin
D0, D0 – D4, D4
Q0, Q0 – Q4, Q4
VBB
Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output.
Pinout: 28-Lead PLCC (Top View)
D3 D4 D4 VCCO Q4 Q4 VCCO
25 24
D3 26
23 22 21 20
19
18 Q3
D2 27
D2 28
17 Q3
16 VCC
VEE 1
15 Q2
VBB 2
14 Q2
D0 3
13 VCCO
D0 4
12 Q1
5 6 7 8 9 10 11
D1 D1 VCCO Q0 Q0 VCCO Q1
* All VCC and VCCO pins are tied together on the die.
5/95
© Motorola, Inc. 1996
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