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MC10231 Datasheet, PDF (1/5 Pages) ON Semiconductor – High Speed Dual Type D Master-Slave Flip-Flop | |||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Speed Dual Type D
Master-Slave Flip-Flop
The MC10231 is a dual masterâslave type D flipâflop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flipâflop
may be clocked separately by holding the common clock in the low state and
using the enable inputs for the clocking function. If the common clock is to be
used to clock the flipâflop, the Clock Enable inputs must be in the low state. In
this case, the enable inputs perform the function of controlling the common
clock.
The output states of the flipâflop change on the positive transition of the
clock. A change in the information present at the data (D) input will not affect the
output information at any other time due to masterâslave construction.
PD = 270 mW typ/pkg (No Load)
tpd = 2 ns typ
tTog= 225 MHz typ
tr, tf = 2.0 ns typ (20%â80%)
LOGIC DIAGRAM
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
Q1
2
Q1
3
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
CE2 11
D2 10
Q2
15
Q2
14
S2 12
CLOCKED TRUTH TABLE
C
D
Qn+1
L
X
Qn
H
L
L
H
H
H
C = CE + CC. A clock H is a clock
transition from a low to a high state.
RâS TRUTH TABLE
R
S
Qn+1
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
MC10231
L SUFFIX
CERAMIC PACKAGE
CASE 620â10
P SUFFIX
PLASTIC PACKAGE
CASE 648â08
FN SUFFIX
PLCC
CASE 775â02
DIP
PIN ASSIGNMENT
VCC1
1
Q1
2
Q1
3
R1
4
S1
5
CE1
6
D1
7
VEE
8
16
VCC2
15
Q2
14
Q2
13
R2
12
S2
11
CE2
10
D2
9
CC
Pin assignment is for DualâinâLine Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6â11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3â202
REV 5
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