MC10186 Datasheet, PDF (1/5 Pages) ON Semiconductor – Hex D Master-Slave Flip-Flop With Reset

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Master-Slave Flip-Flop
With Reset
MC10186
The MC10186 contains six high–speed, master slave type “D” flip–flops.
Clocking is common to all six flip–flops. Data is entered into the master when
the clock is low. Master to slave data transfer takes place on the positive–going
Clock transition. Thus, outputs may change only on a positive–going Clock
transition. A change in the information present at the data (D) input will not affect
the output information any other time due to the master–slave construction of
this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET
ONLY FUNCTIONS WHEN CLOCK IS LOW.
PD = 460 mW typ/pkg (No Load)
ftoggle= 150 MHz (typ)
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
D0 5
2 Q0
D1 6
3 Q1
D2 7
4 Q2
D3 10
13 Q3
D4 11
D5 12
CLOCK 9
RESET 1
VCC = PIN 16
VEE = PIN 8
14 Q4
15 Q5
CLOCKED TRUTH TABLE
RCD
Qn + 1
LLX
Qn
L H* L
L
L H* H
H
HLX
L
*A clock H is a clock transition
from a low to a high state.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
RESET
1
Q0
2
Q1
3
Q2
4
D0
5
D1
6
D2
7
VEE
8
16
VCC
15
Q5
14
Q4
13
Q3
12
D5
11
D4
10
D3
9
CLOCK
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–147
REV 5