MC10175_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Quint Latch

MC10175
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five
D type latches with common reset and a common two–input clock.
Data is transferred on the negative edge of the clock and latched on the
positive edge. The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while
the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state, a change in the
information present at the data inputs will not affect the output
information. The reset input is enabled only when the clock is in the
high state.
• P_D = 400 mW typ/pkg (No Load)
• t_pd = 2.5 ns typ (Data to Output)
• t_r, t_f = 2.0 ns typ (20%–80%)
D0 10
LOGIC DIAGRAM
DQ
CR
14 Q0
D1 12
DQ
CR
15 Q1
D2 13
DQ
CR
2 Q2
D3 9
DQ
CR
3 Q3
D4 5
C0 6
C1 7
RESET 11
DQ
CR
4 Q4
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
TRUTH TABLE
D C0
C1
Reset Q_n+1
LL
L
HL
L
XH
X
XX
H
XH
X
XX
H
X
L
X
H
L
Qn
L
Qn
H
L
H
L
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10175L
AWLYYWW
1
16
MC10175P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10175
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
DIP PIN ASSIGNMENT
V_CC1
1
Q2
2
Q3
3
Q4
4
D4
5
C0
6
C1
7
V_EE
8
16
V_CC2
15
Q1
14
Q0
13
D2
12
D1
11
RESET
10
D0
9
D3
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
Package
Shipping
MC10175L
CDIP–16
25 Units / Rail
MC10175P
PDIP–16
25 Units / Rail
MC10175FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10175/D